1. Field of the Invention
This invention generally relates to a PLL (Phase-Locked Loop) circuit and more particularly to a PLL circuit which employs a carrier signal modulated by PSK (Phase Shift Keying) as an input signal and which obtains a stable oscillation output signal.
2. Description of the Related Art
There has been a PLL circuit of such a type used in a detection circuit when a reception is performed in a non-contact integrated-circuit (IC) card for performing communication by carrying out a PSK modulation, which is described in the Japanese Patent Application No. 7-244738 (not published). FIG. 15 schematically illustrates the configuration of a receiving circuit, which contains a PLL circuit, of this non-contact IC card. Incidentally, in FIG. 15, a circuit for performing a modulation at the time of transmitting is omitted.
In FIG. 15, reference character 1 designates a non-contact IC card; 2 an antenna resonance circuit which is a parallel resonance circuit including an antenna coil 2a and a capacitor 2b; 3 a full-wave bridge rectifying circuit including of rectifying devices 3a to 3d; 4 a switching circuit including N-channel transistors 4a to 4d; 5 an inverter; 6 a Zener diode for obtaining a constant power supply voltage; 7 an energy storage circuit for smoothing a rectified voltage and for storing energy; and Ra a resistor.
Further, reference numeral 8 denotes a comparator; and 9 a D-type flip-flop. These elements compose a circuit for generating a switching signal C to be supplied to the switching circuit 3 that is operative to ground a terminal of the antenna resonance circuit 2, which corresponds to a voltage lower than that at the other terminal thereof. Moreover, reference character 10 represents a PLL circuit; 11 an EX-OR (exclusive OR) circuit; and 12a and 12b D-type flip-flops. These elements compose a detection portion for detecting an occurrence of a phase modulation in an input signal. Furthermore, FIG. 16 illustrates the waveforms of signals respectively flowing through portions of the receiving circuit of FIG. 15.
Next, an operation of the receiving circuit will be briefly described hereinbelow. Reference numeral 0 represents a voltage developed across the antenna resonance circuit 2 (in FIG. 16). When the comparator 8 detects that the signal level of the input signal P becomes lower than the ground level indicated by a dashed line (see FIG. 16), the D-type flip-flop 9 reverses a switching signal Q for causing a switching circuit 4 to ground the terminal of the antenna resonance circuit 2, which corresponds to the lower voltage. Thereby, as is seen from a graph showing the waveform of the input signal P, the terminal of the antenna resonance circuit 2, which corresponds to the lower voltage, is grounded. In contrast, a signal representing the higher voltage level is taken out of the other terminal thereof.
The detection portion including the PLL circuit 10, the EX-OR circuit 11, the D-type flip-flops 12a and 12b produces a reference phase signal from a signal R outputted from the comparator 8 and further detects a change in phase by comparing the phase of this reference phase signal with that of a received signal. The PLL circuit 10 receives the signal R, which indicates that the signal level of the input signal P becomes lower than the ground level, and generates an output signal R' tuned thereto. Then, the frequency of the output signal R' of the PLL circuit 10 is divided by 2 by means of the D-type flip-flop 12b. Further, a resultant signal is employed as a reference phase signal R". Subsequently, an EX-OR 11 carries out an EX-OR between this reference phase signal R" and the switching signal Q. Thereafter, a detection output signal S' is obtained by the D-type flip-flop 12a (for removing so-called "beards" from the signal S) by performing a sampling on the signal S every half of the period of the output signal R' of the PLL circuit 10.
The switching signal Q corresponds to the phase of a received signal. Thereby, an EX-OR between the switching signal Q and the reference phase signal R" is performed. Thus, it is detected whether or not a change in phase of a signal received by performing the sampling every half of the period of the signal.
Namely, the PLL circuit 10 outputs a signal, whose frequency corresponds to the input signal, in such a manner that even when, for example, one of input pulses is omitted similarly as in the case illustrated by the waveform diagrams showing the waveforms of the signals R and R' of FIG. 16, the circuit compensates for the omitted input pulse.
FIG. 17 shows the configuration of an example of the conventional PLL circuit. In FIG. 17 showing the configuration of the PLL circuit 10, reference numeral 20 designates a phase comparator including, for example, NAND-gates 202 to 216; 30 a loop filter including resistors R1 and R2 and a capacitor C1; and 40 a Voltage Controlled Oscillator (hereunder abbreviated as a VCO). Incidentally, this circuit is implemented by a chip, the device No. of which is 74HC4046A.
Thus, the PLL circuit 10 is composed of the phase comparator 20, the loop filter 30 and the VCO 40. The phase comparator 20 generates a voltage according to a difference in phase between the input signal (for instance, the signal R) and the output signal (for example, the signal R') of the VCO 40.
To put this in a little more detail, for instance, in the case that the input signal has a same frequency and a same phase as the output signal of the VCO 40, the duty ratio of pulses of an output signal of the phase comparator 20 is 50%. Further, this duty ratio varies from 50%, which is the center of variation, with a phase lag or a phase lead of the signal. For example, when the duty ratio exceeds 50%, the loop filter 30 is put into a charging state. Thus, the voltage level of the loop filter 30 rises. In contrast, when the duty ratio becomes equal to or less than 50%, the loop filter 30 is put into a discharging state. Thus, the voltage level of the loop filter 30 falls.
An output voltage of this loop filter 30 is a control voltage for the VCO 40. Further, the VCO 40 outputs a signal having a frequency determined in accordance with an input voltage. Furthermore, a feedback control operation is performed in such a way that the differences in frequency and in phase between the input signal R and the output signal R' of the VCO 40 are eliminated.
In the case of the conventional PLL circuit configured as above described, the frequency and phase of the input signal are adjusted to those of the output signal of the VCO, respectively, by repeatedly performing the charging and discharging of the loop filter. Thus, the conventional PLL circuit has encountered a problem that it takes time to put the PLL circuit into a locked state in which the frequency and the phase of the input signal are matched with those of the output signal of the VCO, respectively.